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[VHDL-FPGA-Verilog] FPGA

Description: FPGA交通灯说明： 1. 本程序使用VHDL加原理图方式设计而成。 2. 实验时，使用Quartus II软件完成了工程管理与下载验证，使用max+plus II软件进行了功能仿真。 3. 由于实验当时对原理图文件缺乏足够的认识，导致原原理图以及仿真输出文件已经丢失。现在的工程 RTL视图以及仿真输出波形均是在Quartus II软件下得到的。-FPGA traffic lights shows:1procedures for the use of the VHDL schematic design and.In 2 experiments, using Quartus II software to complete the project management and download validation, use max+plus II software to carry out the function simulation.The 3experiment was due to schematic document lacks enough understanding, resulting in the original diagram and simulation output file is missing. Now the engineering RTL view as well as the simulation output waveform are in Quartus II software under.
Platform: | Size: 455680 | Author: WangQunfeng | Hits:

[VHDL-FPGA-Verilog] eda6

Description: 以Altera公司的MAX+plus II为工具软件，采用Verilog HDL文本输入设计法设计8位二进制加减计数器，生成元件符号-Altera s MAX+plus II tools software, using Verilog HDL text input method to design8 binary addition and subtraction counter, generating element symbol
Platform: | Size: 34816 | Author: 王宇 | Hits:

[Other] verilog_hdl

Description: You can now read the brochure in the Quartus II. Altera ® the Quartus ® II design software is suitable for The most comprehensive single-chip programmable system (SOPC) design environment. If you have previously used MAX + PLUS ® II software, and other design software or ASIC design software and are ready to switch Quartus II software, or if you have some understanding of the Quartus II software, but want to learn more Its functions, this manual is for you. -verilog_hdl Language Tutorial
Platform: | Size: 1344512 | Author: 任耀庭 | Hits:

[VHDL-FPGA-Verilog] Taximeter

Description: 采用VHDL编写出租车计费器系统程序，采用MAX+PLUSⅡ软件作为开发平台，进行了程序仿真，验证设计 实现了出租车计价器的相关功能。-Several current problemsarediscussedandonekindof designscheme for themultifunctional taximeter basedonPIC16F877isprovided. It realizesthenormal pricing. Still it hasthefunctionof ant-i cheating andpower fail safeguard. Itshardwareandsoftwaredesignsare elaborated, and itsfeasibility isverified
Platform: | Size: 388096 | Author: Ruirui | Hits:

[VHDL-FPGA-Verilog] VHDL

Description: 本设计中选用目前应用较广泛的VHDL硬件电路描述语言，实现对路口交通灯系统的控制器的硬件电路描述，在Altera公司的EDA软件平台MAX+PLUSⅡ环境下通过了编译、仿真，并下载到CPLD器件上进行编程制作，实现了交通灯系统的控制过程。-And select and use Description Language applying broader VHDL hardware circuit at present in capital being designed, the hardware circuit coming true to systematic controller of crossing traffic light describes that, have passed compiling , have simulated under EDA of Altera company software platform MAX+ PLUS II environment, download the control procedure having made , realizing traffic light systematically to the programming being in progress on CPLD component.
Platform: | Size: 266240 | Author: 陈金峰 | Hits:

[VHDL-FPGA-Verilog] verilog

Description: Verilog 中文教學 1.簡介 2. Verilog 的模型 3. Verilog 的架構 4. MAX+plus II 的 環境 5. 基本資料型態 6. 輸出入埠的宣告 7. 邏輯閘階層模型的敘述 8. 資料流模型的敘述 9. 行為模型的敘述 10. 編譯命令 11. 循序邏輯電路範例
Platform: | Size: 600064 | Author: bill | Hits:

[VHDL-FPGA-Verilog] askfsk

Description: 通信原理ask、fsk仿真流程，采用max+plus实现-Communication theory ask, FSK simulation processes using max+plus achieve
Platform: | Size: 299008 | Author: lpx_matlab | Hits:

[Windows Develop] MaxPlusII

Description: Max+Plus II 简易用户使用入门指南,适合于初学者。-Max+Plus II
Platform: | Size: 236544 | Author: 痴心绝对 | Hits:

[Other] accumulator

Description: accumulator max plus
Platform: | Size: 5120 | Author: rls1324 | Hits:

[Other] address_register

Description: address register max plus
Platform: | Size: 3072 | Author: rls1324 | Hits:

[Other] data_register

Description: data register max plus
Platform: | Size: 5120 | Author: rls1324 | Hits:

[Other] instruction_register

Description: instruction register max plus
Platform: | Size: 5120 | Author: rls1324 | Hits:

[Other] program_counter

Description: program counter max plus
Platform: | Size: 4096 | Author: rls1324 | Hits:

[VHDL-FPGA-Verilog] MAXPplus-II

Description: MAX+plus II的安装以及破解方法，和大家共享一下，有需要的拿去参考一下。-Installation as well as crack MAX+plus II, and share, there is a need to take a look.
Platform: | Size: 23552 | Author: 陈玉宝 | Hits:

[Other] stopwatch

Description: 24小时计时表和计数译码显示电路的编程，显示秒、分、小时， MAX+plus II 仿真。-24 hours stopwatch and count decoding display circuit programming, display seconds, points, hours, MAX+ plus II simulation.
Platform: | Size: 218112 | Author: 宋辉 | Hits:

[VHDL-FPGA-Verilog] Multi-function-waveform-generator

Description: 本系统应用VHDL语言及MAX+PLUS II仿真软件利用自顶向下的设计思想进行设计，结合示波器加以完成一个可应用于数字系统开发或实验时做输入脉冲信号或基准脉冲信号用的信号发生器，它具结构紧凑，性能稳定，设计结构灵活，方便进行多功能组合的特点，经济实用，成本低廉。具有产生四种基本波形脉冲信号（方波、三角波、锯齿波和正弦波），且脉冲信号输出幅度及输出频率可调，对于方波信号，还可以实现占空比可调。通过软件仿真和硬件测试都得到了预期的结果。-The system using VHDL language and MAX+ PLUS II simulation software using a top-down design ideas to design a combined oscilloscope be completed to do the input pulse signal or reference pulse signal with the signal generator used in digital system development or experimentalwith compact structure, stable performance, flexible structure design, convenient multifunction portfolio characteristics, economical and practical, low cost. Has four basic waveform pulse signal (square wave, triangle wave, sawtooth and sine wave), and the amplitude of the pulse signal output and the output frequency is adjustable, adjustable duty cycle square wave signal can also be achieved. Expected results through software simulation and hardware testing.
Platform: | Size: 1485824 | Author: xinxing | Hits:

[Other] frequency-divider-graphic-design

Description: 数字系统EDA 多级分频器图形设计 熟悉和掌握MAX+PlusⅡ的编译、仿真操作。-The multi-level divider graphic design of digital systems EDA familiar with and master MAX+Plus Ⅱ compilation, simulation operation.
Platform: | Size: 256000 | Author: 王海阔 | Hits:

[Other] Digital-system-EDA

Description: 四位二进制数可预置可逆计数器设计 学习使用MAX+PlusⅡ文本编辑器的模板输入方法,熟悉常用语句的语法现象，掌握VHDL功能描述和结构描述的方法。-Four binary number can be preset the reversible counter design learning using a text editor MAX+Plus Ⅱ template input method, familiar with common statement syntax phenomenon master VHDL functional description and schema.
Platform: | Size: 161792 | Author: 王海阔 | Hits:

[Software Engineering] MAXplus2experimententry

Description: 通信工程专业里MAX+plusⅡ_实验之入门教学。-Teaching Communication Engineering MAX+plus Ⅱ _ experiment entry.
Platform: | Size: 759808 | Author: 陆秋菊 | Hits:

[VHDL-FPGA-Verilog] 24seconds

Description: 24秒倒计时的vhdl程序，采用Max plus -24 seconds countdown vhdl procedures, using Max plus II
Platform: | Size: 406528 | Author: wjk | Hits:
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